DS90UB914A-Q1 Datasheet, PDF (26/61 Pages) Texas Instruments – 25-MHz to 100-MHz 10/12-Bit FPD-Link III Deserializer

DS90UB914A-Q1
SNLS499A – APRIL 2016 – REVISED JUNE 2016
www.ti.com
8.4.4 Clock-Data Recovery Status Flag (LOCK), Output Enable (OEN) and Output State Select
(OSS_SEL)
When PDB is driven HIGH, the Deserializer’s CDR PLL begins locking to the serial input and LOCK is TRI-
STATE or LOW (depending on the value of the OEN setting). After the DS90UB914A-Q1 completes its lock
sequence to the input serial data, the LOCK output is driven HIGH, indicating valid data and clock recovered
from the serial input is available on the parallel bus and PCLK outputs. The states of the outputs are based on
the OEN and OSS_SEL setting (Table 2). See Figure 9.
SERIAL
INPUTS
X
X
X
Static
Static
Active
Active
INPUTS
PDB
OEN
0
X
1
0
1
0
1
1
1
1
1
1
1
1
Table 2. Output States
OUTPUTS
OSS_SEL
LOCK
PASS
DATA, GPIO
X
Z
Z
Z
0
L or H
L
L
1
L or H
Z
Z
0
L
L
L
1
L
Previous State
L
0
H
L
L
1
H
Valid
Valid
CLK
Z
L
Z
L/Osc
(Register Bit Enable)
L
L
Valid
26
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