LAN91C111_11 Datasheet, PDF (97/133 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
DRIVER SEND
Choose B ank Sele ct
Register 2
C a ll A L L O C ATE
A L L O C ATE
Issue "Allocate M emory"
Command to MMU
Read Interrupt Status Register
Exit Driver Send
Ye s
Re ad A llocation Result
R e g is te r
W rite Allocated Packet into
Packet # Register
W rite Address Po inter Register
A llo c a tio n
Passed?
Copy Part of TX Data Packet
into RA M
W rite Source A ddress into
Proper Location
Copy Rem ain ing TX Da ta
Packet in to RA M
Enqueue Packet
No
S to re D a ta B u ffe r Po in te r
Clea r "Re ady fo r Packet" Flag
E nable A llocation Interrupt
S e t "R e a d y fo r Pa cke t" Fla g
Retu rn B u ffers to Upp er L aye r
R e tu r n
Figure 10.5 Drive Send and Allocate Routines
MEMORY PARTITIONING
Unlike other controllers, the LAN91C111 does not require a fixed memory partitioning between transmit
and receive resources. The MMU allocates and de-allocates memory upon different events. An
additional mechanism allows the CPU to prevent the receive process from starving the transmit
memory allocation.
Memory is always requested by the side that needs to write into it, that is: the CPU for transmit or the
MAC for receive. The CPU can control the number of bytes it requests for transmit but it cannot
determine the number of bytes the receive process is going to demand. Furthermore, the receive
SMSC LAN91C111 REV C
97
DATASHEET
Revision 1.92 (06-27-11)