LAN91C111_11 Datasheet, PDF (101/133 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
RELOAD and STORE are set by the user to initiate read and write operations respectively. Polling the
value until read low is used to determine completion. When an EEPROM access is in progress the
STORE and RELOAD bits of CTR will readback as both bits high. No other bits of the LAN91C111 can
be read or written until the EEPROM operation completes and both bits are clear. This mechanism is
also valid for reset initiated reloads.
Note:
If no EEPROM is connected to the LAN91C111, for example for some embedded applications,
the ENEEP pin should be grounded and no accesses to the EEPROM will be attempted.
Configuration, Base, and Individual Address assume their default values upon hardware reset
and the CPU is responsible for programming them for their final value.
SMSC LAN91C111 REV C
101
DATASHEET
Revision 1.92 (06-27-11)