LAN91C111_11 Datasheet, PDF (71/133 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
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8.23 Bank 3 - Management Interface
OFFSET
8
NAME
MANAGEMENT
INTERFACE
TYPE
SYMBOL
READ/WRITE
MGMT
HIGH
BYTE
LOW
BYTE
Reserved
0
MSK_ Reserved Reserved Reserved Reserved Reserved Reserved
CRS100
0
1
1
0
0
1
1
Reserved
MDOE
MCLK
MDI
MDO
0
0
1
1
0
0
MDI Pin
0
MSK_CRS100 - Disables CRS100 detection during transmit in half duplex mode (SWFDUP=0).
MDO - MII Management output. The value of this bit drives the MDO pin.
MDI - MII Management input. The value of the MDI pin is readable using this bit.
MDCLK - MII Management clock. The value of this bit drives the MDCLK pin.
MDOE - MII Management output enable. When high pin MDO is driven, when low pin MDO is tri-
stated.
The purpose of this interface, along with the corresponding pins is to implement MII PHY management
in software.
SMSC LAN91C111 REV C
71
DATASHEET
Revision 1.92 (06-27-11)