LAN91C111_11 Datasheet, PDF (121/133 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
t8
t9
t10
t11
t16
t17A
t18
t20
t21
PARAMETER
A1-A15, AEN, nBE[3:0] Setup to nADS Rising
A1-A15, AEN, nBE[3:0] Hold After nADS Rising
nCYCLE Setup to LCLK Rising
nCYCLE Hold after LCLK Rising (Non-Burst Mode)
W/nR Setup to nCYCLE Active
W/nR Hold after LCLK Rising with nSRDY Active
Data Setup to LCLK Rising (Write)
Data Hold from LCLK Rising (Write)
nSRDY Delay from LCLK Rising
MIN TYP MAX UNITS
8
ns
5
ns
5
ns
3
ns
0
ns
3
ns
15
ns
4
ns
7
ns
Clock
Address, AEN, nBE[3:0]
nADS
W/nR
nCYCLE
Read Data
nSRDY
nRDYRTN
t10
t9
Valid
t8
t16
t11
t23
t20
t24
Valid
t21
t21
Figure 14.9 Synchronous Read Cycle - nVLBUS=0
SMSC LAN91C111 REV C
121
DATASHEET
Revision 1.92 (06-27-11)