LAN91C111_11 Datasheet, PDF (82/133 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
TX_HDX
R
0
10_FDX
R
0
10_HDX
R
0
Reserved
R
0
Reserved
R
0
Reserved
R
0
Reserved
R
0
CSMA
R
0
The bit definitions are analogous to the Auto Negotiation Advertisement Register.
9.6 Register 16. Configuration 1- Structure and Bit Definition
LNKDIS
RW
0
XMTDIS
RW
0
XMTPDN
RW
0
Reserved
RW
0
Reserved
RW
0
BYPSCR
RW
0
UNSCDS
RW
0
EQLZR
RW
0
CABLE
RW
0
RLVL0
RW
0
TLVL3
RW
1
LNKDIS:
XMTDIS:
XMTPDN:
RESERVED:
BYPSCR:
UNSCDS:
TLVL2
RW
0
TLVL1
RW
0
TLVL0
RW
0
TRF1
RW
1
Link Disable
TP Transmit
TP Transmit
Powerdown
RESERVED
Bypass
Scrambler/Descr-
ambler Select
Unscrambled Idle
1 = Receive Link
Detect Function
Disabled (Force Link
Pass)
0 = Normal
1 = TP Transmitter
Disabled
0 = Normal
1 = TP Transmitter
Powered Down
0 = Normal
Reserved, Must be 0
for Proper Operation
1 = Bypass
Scrambler/Descram
bler
0 = No Bypass
1 = Disable
AutoNegotiation with
devices that transmit
unscrambled
TRF0
RW
0
Revision 1.92 (06-27-11)
82
DATASHEET
SMSC LAN91C111 REV C