LAN91C111_11 Datasheet, PDF (24/133 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

7.5.4
10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
MII Packet Data Communication with External PHY
The MIl is a nibble wide packet data interface defined in IEEE 802.3. The LAN91C111 meets all the
MIl requirements outlined in IEEE 802.3 and shown in Figure 7.2.
TX_EN = 0
IDLE
PREAMBLE
PRMBLE
62 BT
START
OF
FRAME
DELIM.
SFD
TX_EN = 1
DATA 1
DATA NIBBLES
DATA 2
DATA N-1
2 BT
DATA N
TX_EN = 0
IDLE
PREAMBLE = [ 1 0 1 0 ... ] 62 BITS LONG
SFD = [ 1 1 ]
DATAn = [ BETWEEN 64-1518 DATA BYTES ]
IDLE = TX_EN = 0
MII
NIBBLE
STREAM
FIRST BIT
MAC's SERIAL BIT STREAM
LSB D0 D1 D2 D3 D4 D5 D6 D7 MSB
FIRST
NIBBLE
SECOND
NIBBLE
TXD0 / RXD0
TXD1 / RXD1
TXD2 / RXD2
TXD3 / RXD3
Figure 7.2 MII Frame Format & MII Nibble Order
The Mll consists of the following signals: four transmit data bits (TXD[3:0]), transmit clock
(TX25),transmit enable (TXEN100), four receive data bits(RXD[3:0]), receive clock(RX25), carrier
sense (CRS100), receive data valid (RX_DV), receive data error (RX_ER), and collision (COL100).
Transmit data is clocked out using the TX25 clock input, while receive data is clocked in using RX25. The
transmit and receive clocks operate at 25 MHz in 100Mbps mode and 2.5 MHz in 10Mbps.
In 100 Mbps mode, the LAN91C111 provides the following interface signals to the PHY:
„ For transmission: TXEN100, TXD0-3, TX25
„ For reception: RX_DV, RX_ER, RXD0-3, RX25
„ For CSMA/CD state machines: CRS100, COL100
A transmission begins by TXEN100 going active (high), and TXD0-TXD3 having the first valid
preamble nibble. TXD0 carries the least significant bit of the nibble (that is the one that would go first
out of the EPH at 100 Mbps), while TXD3 carries the most significant bit of the nibble. TXEN100 and
TXD0-TXD3 are clocked by the LAN91C111 using TX25 rising edges. TXEN100 goes inactive at the
end of the packet on the last nibble of the CRC.
During a transmission, COL100 might become active to indicate a collision. COL100 is asynchronous
to the LAN91C111’s clocks and will be synchronized internally to TX25.
Reception begins when RX_DV (receive data valid) is asserted. A preamble pattern or flag octet will
be present at RXD0-RXD3 when RX_DV is activated. The LAN91C111 requires no training sequence
Revision 1.92 (06-27-11)
24
DATASHEET
SMSC LAN91C111 REV C