LAN91C111_11 Datasheet, PDF (75/133 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
REGISTER ADDRESS
16
17
18
19
20
PHY Register Description
REGISTER NAME
Configuration 1
Configuration 2
Status Output
Mask
Reserved
<Idle>
<Start>
<Read>
Table 9.1 MII Serial Frame Structure
<Write> <PHY Addr.>
<REG.Addr.>
IDLE ST[1:0] READ WRITE
PHYAD[4:0]
REGAD[4:0]
<Turnaround>
TA[1:0]
<Data>
D[15:0]
D[15:0]
↓
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 16
Register 17
Register 18
Register 19
Register 20
Control
Status
PHY ID#1
PHY ID#2
AutoNegotiation Advertisement
AutoNegotiation Remote End Capability
Configuration 1
Configuration 2
Status Output
Mask
Reserved
SYMBOL
IDLE
ST1
ST0
READ
WRITE
NAME
Idle Pattern
Start Bits
DEFINITION
R/W
These bits are an idle pattern. Device will not initiate an MI cycle until W
it detects at least 32 1's
When ST[1:0]=01, a MI Serial Port access cycle starts.
W
Read Select 1 = Read Cycle
W
Write Select 1 = Write Cycle
W
SMSC LAN91C111 REV C
75
DATASHEET
Revision 1.92 (06-27-11)