LAN91C111_11 Datasheet, PDF (133/133 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
Chapter 16 Datasheet Revision History
Table 16.1 Customer Revision History
REVISION LEVEL & DATE SECTION/FIGURE/ENTRY
CORRECTION
Rev. 1.92
(06-27-11)
Rev. 1.92
(04-27-11)
Rev. 1.92
(04-27-11)
Rev. 1.92
(04-27-11)
Rev. 1.91
(06-01-09)
Rev. 1.9
(07-17-08)
Rev. 1.9
(07-17-08)
Rev. 1.9
(07-17-08)
Rev. 1.9
(07-17-08)
Rev. 1.9
(07-17-08)
Rev. 1.9
(07-17-08)
Rev. 1.9
(07-17-08)
Section 7.7.17, "PHY
Powerdown," on page 41
Added note stating that the PDN bit must not be
set when the device is in external PHY mode.
Table 10.1, “Typical Flow Of
Events For Placing Device
In Low Power Mode,” on
page 88
Added note to step 6 stating that the bit (PDN)
must not be set when the device is in external PHY
mode.
Table 10.2, “Flow Of Events
For Restoring Device In
Normal Power Mode,” on
page 89
Added note to step 3 stating that the step is only
performed when the device is in internal PHY
mode.
Table 9.1, “Register 0.
Control Register,” on
page 78
Added note to PDN bit definition stating that the bit
must not be set when the device is in external PHY
mode.
The following ordering information has been removed: “LAN91C111-NC,
LAN91C111i-NC (Industrial Temperature) for 128 pin QFP packages”,
“LAN91C111-NE, LAN91C111i-NE (Industrial Temperature) for 128-pin TQFP
packages” as these has been discontinued.
All
Updated document references to Rev. C.
Section 13.1, "Maximum
Guaranteed Ratings*," on
page 110
Cover
Section 8.24, "Bank 3 -
Revision Register," on
page 72
Table 14.3, “Asynchronous
Cycle - nADS=0,” on
page 117
Section 10.4, "Typical Flow
of Event For Receive," on
page 91
Section 7.7.14, "Receive
Polarity Correction," on
page 40
Fixed commercial temp range to state “0°C to
+70°C for LAN91C111”
Added bullet: “Commercial Temperature Range
from 0°C to 70°C (LAN91C111)”
Changed REV default from “0001” to “0010”
Changed T1A time in table under figure from 10nS
min to 2nS min.
In step 4, changed last sentence from “If CRC is
incorrect the packet memory is released and no
interrupt will occur.”, to “The RCV_BAD bit of the
Bank 1 Control Register controls whether or not to
generate interrupts when bad CRC packets are
received.”
Added note at end of 10 Mbps subsection stating
“The first 3 received packets must be discarded
after the correction of a reverse polarity condition.”
SMSC LAN91C111 REV C
133
DATASHEET
Revision 1.92 (06-27-11)