LAN91C111_11 Datasheet, PDF (106/133 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
Table 12.2 High-End ISA or Non-Burst EISA Machines Signal Connectors (continued)
ISA BUS
SIGNAL
nIOWR
IOCHRDY
RESET
A0
nSBHE
IRQn
D0-D15
LAN91C111
SIGNAL
nWR
ARDY
RESET
nBE0
nBE1
INTR0
D0-D15
NOTES
I/O Write strobe - asynchronous write access. Address is valid before
leading edge. Data is latched on trailing edge.
This signal is negated on leading nRD, nWR if necessary. It is then
asserted on CLK rising edge after the access condition is satisfied.
16 bit data bus. The bus byte(s) used to access the device are a function
of nBE0 and nBE1:
nBE0
0
0
1
nBE1
0
1
0
D0-D7
Lower
Lower
Not used
D8-D15
Upper
Not used
Upper
nIOCS16
nLDEV buffered
UNUSED PINS
GND
nADS
VCC
nBE2, nBE3,
nCYCLE, W/nR,
nRDYRTN, LCLK
Not used = tri-state on reads, ignored on writes
nLDEV is a totem pole output. Must be buffered using an open collector
driver. nLDEV is active on valid decodes of A15-A4 and AEN=0.
No upper word access.
Revision 1.92 (06-27-11)
106
DATASHEET
SMSC LAN91C111 REV C