LAN91C111_11 Datasheet, PDF (84/133 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
APOLDIS:
JABDIS:
MREG:
INTMDIO:
Reserved:
Auto Polarity
Disable
1 = Auto
Polarity
Correction
Function
Disabled
1 = Auto
Polarity
Correction
Function
Disabled
0 = Normal
0 = Normal
Jabber Disable
Select
1 = Jabber
Disabled RW
1 = Jabber
Disabled
0 = Enabled
0 = Enabled
Multiple Register 1 = Multiple
Access Enable Register Access
Enabled
0 = No Multiple
Register Access
0 = No
Multiple
Register
Access
Interrupt
Scheme Select
1 = Interrupt
Signaled With
MDIO Pulse
During Idle
1 = Interrupt
Signaled
With MDIO
Pulse During
Idle
0 = Interrupt
Not Signaled
On MDIO
0 = Interrupt
Not Signaled
On MDIO
Reserved for
Factory Use
9.8 Register 18. Status Output - Structure and Bit Definition
INT
LNKFAIL
LOSSSYNC
CWRD
R
R/LT
R/LT
R/LT
0
0
0
0
SSD
R/LT
0
ESD
R/LT
0
RPOL
R/LT
0
JAB
R/LT
0
SPDDET
R/LT
1
DPLXDET
R/LT
0
Reserved
R
0
Reserved
R
0
Reserved
R
0
Reserved
R
0
Reserved
R
0
Reserved
R
0
Revision 1.92 (06-27-11)
84
DATASHEET
SMSC LAN91C111 REV C