LAN91C111_11 Datasheet, PDF (76/133 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
SYMBOL
PHYAD[4:0]
REGAD[4:0]
NAME
Physical
Device
Address
Register
Address
TA1
Turnaround
TA0
Time
D[15:0]....
Data
DEFINITION
R/W
PHYSICAL ADDRESS
R
If REGAD[4:0] = 00000-11110, these bits determine the specific
W
register from which D[15:0] is read/written. If multiple register access
is enabled and REGAD[4:0] = 11111, all registers are read/written in
a single cycle.
These bits provide some turnaround time for MDIO
R/W
When READ = 1, TA[1:0] = Z0
When WRITE = 1, TA[1:0] = 10
The turnaround time is a 2 bit time spacing between the Register
Address field and the Data field of a management frame to avoid
contention during a read transaction. For a read transaction, both the
STA and the PHY shall remain in a high impedance state for the first
bit time of the turnaround. The PHY shall drive a zero bit during the
second bit time of the turnaround of a read transaction. During a
write transaction, the STA shall drive a one bit for the first bit time of
the turnaround and a zero bit for the second bit time of the
turnaround.
These 16 bits contain data to/from one of the eleven registers
Any
selected by register address bits REGAD[4:0].
Revision 1.92 (06-27-11)
76
DATASHEET
SMSC LAN91C111 REV C