LAN91C111_11 Datasheet, PDF (57/133 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
8.13 Bank 1 - Individual Address Registers
OFFSET
4 THROUGH 9
NAME
INDIVIDUAL ADDRESS
REGISTERS
TYPE
READ/WRITE
SYMBOL
IAR
These registers are loaded starting at word location 20h of the EEPROM upon hardware reset or
EEPROM reload. The registers can be modified by the software driver, but a STORE operation will not
modify the EEPROM Individual Address contents. Bit 0 of Individual Address 0 register corresponds
to the first bit of the address on the cable.
LOW
BYTE
ADDRESS 0
0
0
0
0
0
0
0
0
HIGH
BYTE
ADDRESS 1
0
0
0
0
0
0
0
0
LOW
BYTE
ADDRESS 2
0
0
0
0
0
0
0
0
HIGH
BYTE
ADDRESS 3
0
0
0
0
0
0
0
0
LOW
BYTE
ADDRESS 4
0
0
0
0
0
0
0
0
HIGH
BYTE
ADDRESS 5
0
0
0
0
0
0
0
0
SMSC LAN91C111 REV C
57
DATASHEET
Revision 1.92 (06-27-11)