LAN91C111_11 Datasheet, PDF (91/133 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
S/W DRIVER
MAC SIDE
4 ISSUE "ENQUEUE PACKET NUMBER TO TX FIFO"
- This command writes the number present in the
Packet Number Register into the TX FIFO. The
transmission is now enqueued. No further CPU
intervention is needed until a transmit interrupt is
generated.
5
The enqueued packet will be transferred to the MAC
block as a function of TXENA (nTCR) bit and of the
deferral process (1/2 duplex mode only) state.
6
Transmit pages are released by transmit completion.
7
The MAC generates a TXEMPTY interrupt upon a
completion of a sequence of enqueued packets.
If a TX failure occurs on any packets, TX INT is
generated and TXENA is cleared, transmission
sequence stops. The packet number of the failure
packet is presented at the TX FIFO PORTS Register.
8 SERVICE INTERRUPT – Read Interrupt Status
Register, exit the interrupt service routine.
Option 1) Release the packet.
Option 2) Check the transmit status in the EPH
STATUS Register, write the packet number of the
current packet to the Packet Number Register, re-
enable TXENA, then go to step 4 to start the TX
sequence again.
10.4 Typical Flow of Event For Receive
S/W DRIVER
1 ENABLE RECEPTION - By setting the RXEN bit.
2
3
MAC SIDE
A packet is received with matching address. Memory
is requested from MMU. A packet number is
assigned to it. Additional memory is requested if
more pages are needed.
The internal DMA logic generates sequential
addresses and writes the receive words into memory.
The MMU does the sequential to physical address
translation. If overrun, packet is dropped and
memory is released.
SMSC LAN91C111 REV C
91
DATASHEET
Revision 1.92 (06-27-11)