LAN91C111_11 Datasheet, PDF (89/133 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
Table 10.1 Typical Flow Of Events For Placing Device In Low Power Mode (continued)
S/W DRIVER
CONTROLLER FUNCTION
9
Ethernet MAC gates the RX Clock, TX clock derived
from the Internal PHY. The EPH Clock is also
disabled.
10 The Ethernet MAC is now in low power mode. The
Host may access all Runtime IO mapped registers.
All IO registers are still accessible. However, the
Host should not read or write to the registers with
the exception of:
Configuration Register
Control Register
Bank Register
Table 10.2 Flow Of Events For Restoring Device In Normal Power Mode
S/W DRIVER
CONTROLLER FUNCTION
1 Write and set (1) the “EPH Power EN” Bit, located in
the configuration register, Bank 1 Offset 0.
2
Ethernet MAC Enables the RX Clock, TX clock
derived from the Internal PHY. The EPH Clock is
also enabled.
3 Write the PDN bit in PHY MI Register 0 to 0
The PHY is then set in isolation mode (MII_DIS bit
Note: Only performed when device is in internal
PHY mode.
is set). Need to clear this MII_DIS bit; and, need to
wait for 500 ms for the PHY to restore normal.
4
Internal PHY entered normal operation mode
5 Issue MMU Reset Command
6 Restore Device Register Level Context.
7 Enable Transmitter – Set the TXENA bit of the
Transmit Control Register
8 Enable Receiver – Set (1) the RXEN bit of the
Receive Control Register.
9
Ethernet MAC can now transmit Ethernet Packets.
Ethernet MAC is now able to receive Packets.
Ethernet MAC is now restored for normal operation.
10.2 Typical Flow of Events for Transmit (Auto Release = 0)
S/W DRIVER
MAC SIDE
1 ISSUE ALLOCATE MEMORY FOR TX - N BYTES -
the MMU attempts to allocate N bytes of RAM.
2 WAIT FOR SUCCESSFUL COMPLETION CODE -
Poll until the ALLOC INT bit is set or enable its mask
bit and wait for the interrupt. The TX packet number
is now at the Allocation Result Register.
SMSC LAN91C111 REV C
89
DATASHEET
Revision 1.92 (06-27-11)