LAN91C111_11 Datasheet, PDF (22/133 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

7.5.2
7.5.3
10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
from the PHY registers. Timing and framing for each management command is to be generated by
the CPU (host).
The MAC and external PHY communicate via MDIO and MDC of the MII Management serial interface.
MDIO:Management Data input/output. Bi-directional between MAC and PHY that carries management
data. All control and status information sent over this pin is driven and sampled synchronously to the
rising edge of MDC signal.
MDC:Management Data Clock. Sourced by the MAC as a timing reference for transfer of information
on the MDIO signal. MDC is a periodic signal with no maximum high or low times. The minimum high
and low times should be 160ns each and the minimum period of the signal should be 400ns. These
values are regardless of the nominal period of the TX and RX clocks.
Management Data Timing
A timing diagram for a Ml serial port frame is shown in Figure 7.1. The Ml serial port is idle when at
least 32 continuous 1's are detected on MDIO and remains idle as long as continuous 1's are detected.
During idle, MDIO is in the high impedance state. When the Ml serial port is in the idle state, a 01
pattern on the MDIO initiates a serial shift cycle. Data on MDIO is then shifted in on the next 14 rising
edges of MDC (MDIO is high impedance). If the register access mode is not enabled, on the next 16
rising edges of MDC, data is either shifted in or out on MDIO, depending on whether a write or read
cycle was selected with the bits READ and WRITE. After the 32 MDC cycles have been completed,
one complete register has been read/written, the serial shift process is halted, data is latched into the
device, and MDIO goes into high impedance state. Another serial shift cycle cannot be initiated until
the idle condition (at least 32 continuous 1's) is detected.
MI Serial Port Frame Structure
The structure of the PHY serial port frame is shown in Table 9.1 and timing diagram of a frame is
shown in Figure 7.1. Each serial port access cycle consists of 32 bits (or 192 bits if multiple register
access is enabled and REGAD[4:0]=11111), exclusive of idle. The first 16 bits of the serial port cycle
are always write bits and are used for addressing. The last 16/176 bits are from one/all of the 11 data
registers.
The first 2 bit in Table 9.1and Figure 7.1 are start bits and need to be written as a 01 for the serial port
cycle to continue. The next 2 bits are a read and write bit which determine if the accessed data register
bits will be read or write. The next 5 bits are device addresses. The next 5 bits are register address
select bits, which select one of the five data registers for access. The next 1 bit is a turnaround bit
which is not an actual register bit but extra time to switch MDIO from write to read if necessary, as
shown in Figure 7.1. The final 16 bits of the PHY Ml serial port cycle (or 176 bits if multiple register
access is enabled and REGAD[4:0]=11111) come from the specific data register designated by the
register address bits REGAD[4:0].
Revision 1.92 (06-27-11)
22
DATASHEET
SMSC LAN91C111 REV C