LAN91C111_11 Datasheet, PDF (51/133 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
8.8
ABORT_ENB - Enables abort of receive when collision occurs. Defaults low. When set, the
LAN91C111 will automatically abort a packet being received when the appropriate collision input is
activated. This bit has no effect if the SWFDUP bit in the TCR is set.
STRIP_CRC - When set, it strips the CRC on received frames. As a result, both the Byte Count and
the frame format do not contain the CRC. When clear, the CRC is stored in memory following the
packet. Defaults low.
RXEN - Enables the receiver when set. If cleared, completes receiving current frame and then goes
idle. Defaults low on reset.
ALMUL - When set accepts all multicast frames (frames in which the first bit of DA is '1'). When clear
accepts only the multicast frames that match the multicast table setting. Defaults low.
PRMS - Promiscuous mode. When set receives all frames. Does not receive its own transmission
unless it is in Full Duplex!
RX_ABORT - This bit is set if a receive frame was aborted due to length longer than 2K bytes. The
frame will not be received. The bit is cleared by RESET or by the CPU writing it low.
Reserved - Must be 0.
Bank 0 - Counter Register
OFFSET
6
NAME
COUNTER REGISTER
TYPE
READ ONLY
SYMBOL
ECR
Counts four parameters for MAC statistics. When any counter reaches 15 an interrupt is issued. All
counters are cleared when reading the register and do not wrap around beyond 15.
HIGH
BYTE
LOW
BYTE
NUMBER OF EXC. DEFFERED TX
0
0
0
0
MULTIPLE COLLISION COUNT
0
0
0
0
NUMBER OF DEFFERED TX
0
0
0
0
SINGLE COLLISION COUNT
0
0
0
0
Each four bit counter is incremented every time the corresponding event, as defined in the EPH
STATUS REGISTER bit description, occurs. Note that the counters can only increment once per
enqueued transmit packet, never faster, limiting the rate of interrupts that can be generated by the
counters. For example if a packet is successfully transmitted after one collision the SINGLE
COLLISION COUNT field is incremented by one. If a packet experiences between 2 to 16 collisions,
the MULTIPLE COLLISION COUNT field is incremented by one. If a packet experiences deferral the
NUMBER OF DEFERRED TX field is incremented by one, even if the packet experienced multiple
deferrals during its collision retries.
The COUNTER REGISTER facilitates maintaining statistics in the AUTO RELEASE mode where no
transmit interrupts are generated on successful transmissions.
Reading the register in the transmit service routine will be enough to maintain statistics.
SMSC LAN91C111 REV C
51
DATASHEET
Revision 1.92 (06-27-11)