LAN91C111_11 Datasheet, PDF (119/133 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
t22
t22A
PARAMETER
nCYCLE Setup to LCLK Rising
nCYCLE Hold After LCLK Rising
MIN TYP MAX UNITS
5
ns
10
ns
Clock
nDATACS
W/nR
nCYCLE
Read Data
nRDYRTN
t17 t12
t14
t19
a
b
t15
t12A
t17A
t19
c
Figure 14.6 Burst Read Cycles - nVLBUS=1
PARAMETER
t12 nDATACS Setup to LCLK Rising
t12A nDATACS Hold after LCLK Rising
t14 nRDYRTN Setup to LCLK Falling
t15 nRDYRTN Hold after LCLK Falling
t17 W/nR Setup to LCLK Falling
t17A W/nR Hold After LCLK Falling
t19 Data Delay from LCLK Rising (Read)
MIN TYP MAX UNITS
20
ns
0
ns
10
ns
10
ns
15
ns
3
ns
5
15
ns
SMSC LAN91C111 REV C
119
DATASHEET
Revision 1.92 (06-27-11)