LAN91C111_11 Datasheet, PDF (46/133 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
8.3
I/O Space
The base I/O space is determined by the IOS0-IOS2 inputs and the EEPROM contents. To limit the
I/O space requirements to 16 locations, the registers are assigned to different banks. The last word of
the I/O area is shared by all banks and can be used to change the bank in use. Registers are
described using the following convention:
OFFSET
NAME
TYPE
SYMBOL
HIGH
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
BYTE
X
X
X
X
X
X
X
X
LOW
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
BYTE
X
X
X
X
X
X
X
X
FFSET - Defines the address offset within the IOBASE where the register can be accessed at,
provided the bank select has the appropriate value.
The offset specifies the address of the even byte (bits 0-7) or the address of the complete word.
The odd byte can be accessed using address (offset + 1).
Some registers (like the Interrupt Ack., or like Interrupt Mask) are functionally described as two eight
bit registers, in that case the offset of each one is independently specified.
Regardless of the functional description, all registers can be accessed as doublewords, words or bytes.
The default bit values upon hard reset are highlighted below each register.
BANK0
0
TCR
2
EPH STATUS
4
RCR
6
COUNTER
8
MIR
A
RPCR
C
RESERVED
E
BANK
Table 8.1 Internal I/O Space Mapping
BANK1
CONFIG
BASE
IA0-1
IA2-3
IA4-5
GENERAL PURPOSE
CONTROL
BANK
BANK2
MMU COMMAND
PNR
FIFO PORTS
POINTER
DATA
DATA
INTERRUPT
BANK
BANK3
MT0-1
MT2-3
MT4-5
MT6-7
MGMT
REVISION
RCV
BANK
A special BANK (BANK7) exists to support the addition of external registers.
Revision 1.92 (06-27-11)
46
DATASHEET
SMSC LAN91C111 REV C