LAN91C111_11 Datasheet, PDF (115/133 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
Chapter 14 Timing Diagrams
Address, AEN, nBE[3:0]
nADS
Read Data
nRD, nWR
Write Data
t2
Valid
t3
t4
Valid
t6
t1
t5
t5A
Valid
Figure 14.1 Asynchronous Cycle - nADS=0
PARAMETER
MIN TYP MAX UNITS
t1
A1-A15, AEN, nBE[3:0] Valid to nRD, nWR Active
2
t2
A1-A15, AEN, nBE[3:0] Hold After nRD, nWR Inactive (Assuming 5
nADS Tied Low)
t3
nRD Low to Valid Data
t4
nRD High to Data Invalid
2
t5
Data Setup to nWR Inactive
10
t5A
Data Hold After nWR Inactive
5
t6
nRD Strobe Width
15
ns
ns
15
ns
15
ns
ns
ns
ns
SMSC LAN91C111 REV C
115
DATASHEET
Revision 1.92 (06-27-11)