LAN91C111_11 Datasheet, PDF (48/133 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
8.5 Bank 0 - Transmit Control Register
OFFSET
0
NAME
TRANSMIT CONTROL
REGISTER
TYPE
READ/WRITE
SYMBOL
TCR
This register holds bits programmed by the CPU to control some of the protocol transmit options.
HIGH
BYTE
LOW
BYTE
SWFDUP
0
PAD_EN
Reserved
0
Reserved
EPH
LOOP
0
Reserved
STP
SQET
0
Reserved
FDUPLX
0
Reserved
MON_
CSN
0
FORCOL
Reserved
0
LOOP
NOCRC
0
TXENA
0
0
0
0
0
0
0
0
SWFDUP - Enables Switched Full Duplex mode. In this mode, transmit state machine is inhibited from
recognizing carrier sense, so deferrals will not occur. Also inhibits collision count, therefore, the
collision related status bits in the EPHSR are not valid (CTR_ROL, LATCOL, SQET, 16COL, MUL COL,
and SNGL COL). Uses COL100 as flow control, limiting backoff and jam to 1 clock each before inter-
frame gap, then retry will occur after IFG. If COL100 is active during preamble, full preamble will be
output before jam. When SWFDUP is high, the values of FDUPLX and MON_CSN have no effect.
EPH_LOOP - Internal loopback at the EPH block. Serial data is internally looped back when set.
Defaults low. When EPH_LOOP is high the following transmit outputs are forced inactive: TXD0-TXD3
= 0h, TXEN100 = 0. The following and external inputs are blocked: CRS100=0, COL100=0, RX_DV=
RX_ER=0.
STP_SQET - STP_SQET - Stop transmission on SQET error. If this bit is set, LAN91C111 will stop
and disable the transmitter on SQE test error. If the external SQET generator on the network generates
the SQET pulse during the IPG (Inter Frame Gap), this bit will not be set and subsequent transmits
will occur as in the case of implementing “Auto Release” for multiple transmit packets. If this bit is
cleared, then the SQET bit in the EPH Status register will be cleared. Defaults low.
FDUPLX - When set the LAN91C111 will cause frames to be received if they pass the address filter
regardless of the source for the frame. When clear the node will not receive a frame sourced by itself.
This bit does not control the duplex mode operation, the duplex mode operation is controlled by the
SWFDUP bit.
MON_CSN - When set the LAN91C111 monitors carrier while transmitting. It must see its own carrier
by the end of the preamble. If it is not seen, or if carrier is lost during transmission, the transmitter
aborts the frame without CRC and turns itself off and sets the LOST CARR bit in the EPHSR. When
this bit is clear the transmitter ignores its own carrier. Defaults low. Should be 0 for MII operation.
NOCRC - Does not append CRC to transmitted frames when set. Allows software to insert the desired
CRC. Defaults to zero, namely CRC inserted.
PAD_EN - When set, the LAN91C111 will pad transmit frames shorter than 64 bytes with 00. For TX,
CPU should write the actual BYTE COUNT before padded by the LAN91C111 to the buffer RAM,
excludes the padded 00. When this bit is cleared, the LAN91C111 does not pad frames.
FORCOL - When set, the FORCOL bit will force a collision by not deferring deliberately. This bit is set
and cleared only by the CPU. When TXENA is enabled with no packets in the queue and while the
FORCOL bit is set, the LAN91C111 will transmit a preamble pattern the next time a carrier is seen on
Revision 1.92 (06-27-11)
48
DATASHEET
SMSC LAN91C111 REV C