LAN91C111_11 Datasheet, PDF (67/133 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
These bits automatically latch upon changing state and stay latched until they are read. When they
are read, the bits that caused the interrupt to happen are updated to their current value. The MDINT
bit will be cleared by writing the acknowledge register with MDINT bit set.
Reserved - Must be 0
EPH INT - Set when the Ethernet Protocol Handler section indicates one out of various possible
special conditions. This bit merges exception type of interrupt sources, whose service time is not
critical to the execution speed of the low level drivers. The exact nature of the interrupt can be obtained
from the EPH Status Register (EPHSR), and enabling of these sources can be done via the Control
Register. The possible sources are:
LINK - Link Test transition
CTR_ROL - Statistics counter roll over
TXENA cleared - A fatal transmit error occurred forcing TXENA to be cleared. TX_SUC will be low and
the specific reason will be reflected by the bits:
„ SQET - SQE Error
„ LOST CARR - Lost Carrier
„ LATCOL - Late Collision
„ 16COL - 16 collisions
Any of the above interrupt sources can be masked by the appropriate ENABLE bits in the Control
Register.
1. 1) LE ENABLE (Link Error Enable), 2) CR ENABLE (Counter Roll Over), 3) TE ENABLE (Transmit
Error Enable)
EPH INT will only be cleared by the following methods:
„ Clearing the LE ENABLE bit in the Control Register if an EPH interrupt is caused by a LINK_OK
transition.
„ Reading the Counter Register if an EPH interrupt is caused by statistics counter roll over.
„ Setting TXENA bit high if an EPH interrupt is caused by any of the fatal transmit error listed above
(3.1 to 3.5).
RX_OVRN INT - Set when 1) the receiver aborts due to an overrun due to a failed memory allocation,
2) the receiver aborts due to a packet length of greater than 2K bytes, or 3) the receiver aborts due
to the RCV DISCRD bit in the RCV register set. The RX_OVRN INT bit latches the condition for the
purpose of being polled or generating an interrupt, and will only be cleared by writing the acknowledge
register with the RX_OVRN INT bit set.
ALLOC INT - Set when an MMU request for TX ram pages is successful. This bit is the complement
of the FAILED bit in the ALLOCATION RESULT register. The ALLOC INT bit is cleared by the MMU
when the next allocation request is processed or allocation fails.
TX EMPTY INT - Set if the TX FIFO goes empty, can be used to generate a single interrupt at the
end of a sequence of packets enqueued for transmission. This bit latches the empty condition, and
the bit will stay set until it is specifically cleared by writing the acknowledge register with the TX EMPTY
INT bit set. If a real time reading of the FIFO empty is desired, the bit should be first cleared and then
read.
The TX_EMPTY MASK bit should only be set after the following steps:
„ A packet is enqueued for transmission
„ The previous empty condition is cleared (acknowledged)
SMSC LAN91C111 REV C
67
DATASHEET
Revision 1.92 (06-27-11)