LAN91C111_11 Datasheet, PDF (47/133 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
8.4 Bank Select Register
OFFSET
NAME
TYPE
E
BANK SELECT REGISTER READ/WRITE
SYMBOL
BSR
HIGH
BYTE
LOW
BYTE
Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
0
0
1
1
0
0
1
1
BS2
BS1
BS0
X
X
X
X
X
0
0
0
BS2, BS1, BS0 Determine the bank presently in use. This register is always accessible and is used
to select the register bank in use.
The upper byte always reads as 33h and can be used to help determine the I/O location of the
LAN91C111.
The BANK SELECT REGISTER is always accessible regardless of the value of BS0-2
Note:
The bank select register can be accessed as a doubleword at offset 0x0Ch, as a word at offset
0x0Eh, or as a byte at offset 0x0Eh, A doubleword write to offset 0x0Ch will write the BANK
SELECT REGISTER but will not write the registers 0x0Ch and 0x0Dh, but will only write to
register 0x0Eh
BANK 7 has no internal registers other than the BANK SELECT REGISTER itself. On valid cycles
where BANK7 is selected (BS0=BS1=BS2=1), and A3=0, nCSOUT is activated to facilitate
implementation of external registers.
Note: BANK7 does not exist in LAN91C9x devices. For backward S/W compatibility BANK7 accesses
should be done if the Revision Control register indicates the device is the LAN91C111.
Bank 7 is a new register Bank to the SMSC LAN91C111 device. This bank has extended registers that
allow the extended feature set of the SMSC LAN91C111.
SMSC LAN91C111 REV C
47
DATASHEET
Revision 1.92 (06-27-11)