LAN91C111_11 Datasheet, PDF (107/133 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
ISA BUS
A1-A15, AEN
RESET
VCC
D0-D15
IRQ
nIORD
nIOWR
A0
nSBHE
A1-A15, AEN
RESET
nBE2, nBE3
D0-D15
INTR0
nRD
nWR
nBE0
nBE1
LAN91C111
nLDEV
nIOCS16
O.C.
Figure 12.2 LAN91C111 on ISA BUS
EISA 32 BIT SLAVE
On EISA the LAN91C111 is accessed as a 32 bit I/O slave, along with a Slave DMA type "C" data
path option. As an I/O slave, the LAN91C111 uses asynchronous accesses. In creating nRD and nWR
inputs, the timing information is externally derived from nCMD edges. Given that the access will be at
least 1.5 to 2 clocks (more than 180ns at least) there is no need to negate EXRDY, simplifying the
EISA interface implementation. As a DMA Slave, the LAN91C111 accepts burst transfers and is able
to sustain the peak rate of one doubleword every BCLK. Doubleword alignment is assumed for DMA
transfers. The LAN91C111 will sample EXRDY and postpone DMA cycles if the memory cycle solicits
wait states.
EISA BUS
SIGNAL
LA2-LA15
M/nIO
AEN
Table 12.3 EISA 32 Bit Slave Signal Connections
LAN91C111
SIGNAL
A2-A15
AEN
NOTES
Address bus used for I/O space and register decoding, latched by
nADS (nSTART) trailing edge.
Qualifies valid I/O decoding - enabled access when low. These
signals are externally ORed. Internally the AEN pin is latched by
nADS rising edge and transparent while nADS is low.
SMSC LAN91C111 REV C
107
DATASHEET
Revision 1.92 (06-27-11)