LAN91C111_11 Datasheet, PDF (66/133 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
8.21 Bank 2 - Interrupt Status Registers
OFFSET
C
NAME
INTERRUPT STATUS
REGISTER
TYPE
READ ONLY
SYMBOL
IST
MDINT
0
Reserved
0
EPH INT
0
RX_OVRN ALLOC INT TX EMPTY
INT
INT
0
0
1
TX INT
0
RCV INT
0
OFFSET
C
NAME
INTERRUPT
ACKNOWLEDGE
REGISTER
TYPE
SYMBOL
WRITE ONLY
IST
MDINT
Reserved
RX_OVRN
INT
TX EMPTY
INT
TX INT
OFFSET
D
NAME
INTERRUPT MASK
REGISTER
TYPE
SYMBOL
READ/WRITE
MSK
MDINT
MASK
0
Reserved
0
EPH INT
MASK
0
RX_OVRN
INT
MASK
ALLOC INT
MASK
TX EMPTY
INT
MASK
0
0
0
TX INT
MASK
0
RCV INT
MASK
0
This register can be read and written as a word or as two individual bytes.
The Interrupt Mask Register bits enable the appropriate bits when high and disable them when low. A
MASK bit being set will cause a hardware interrupt.
MDINT - Set when the following bits in the PHY MI Register 18 (Serial Port Status Output Register)
change state.
1. LNKFAIL, 2) LOSSSYNC, 3) CWRD, 4) SSD, 5) ESD, 6) PROL, 7) JAB, 8) SPDDET, 9) DPLXDET.
Revision 1.92 (06-27-11)
66
DATASHEET
SMSC LAN91C111 REV C