LAN91C111_11 Datasheet, PDF (28/133 Pages) SMSC Corporation – 10/100 Non-PCI Ethernet Single Chip MAC + PHY

10/100 Non-PCI Ethernet Single Chip MAC + PHY
Datasheet
SYMBOL NAME
7
8
9
A
B
C
D
E
F
I
J
K
T
R
H
---
Table 7.1 4B/5B Symbol Mapping (continued)
DESCRIPTION
Data 7
Data 8
Data 9
Data A
Data B
Data C
Data D
Data E
Data F
Idle
SSD #1
SSD #2
ESD #1
ESD #2
Halt
Invalid codes
5B CODE
01111
10010
10011
10110
10111
11010
11011
11100
11101
11111
11000
10001
01101
00111
00100
All others*
4B CODE
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0101
0101
0000
0000
Undefined
0000*
* These 5B codes are not used. For decoder, these 5B codes are decoded to 4B 0000. For encoder,
4B 0000 is encoded to 5B 11110, as shown in symbol Data 0.
The 4B5B decoder detects SSD, ESD and codeword errors in the incoming data stream as specified
in IEEE 802.3. These errors are indicated by asserting RX_ER output while the errors are being
transmitted across RXD[3:0], and they are also indicated in the serial port by setting SSD, ESD, and
codeword error bits in the PHY MI serial port Status Output register.
Manchester Decoder - 10 Mbps
In Manchester coded data, the first half of the data bit contains the complement of the data, and the
second half of the data bit contains the true data. The Manchester decoder in the LAN91C111 converts
the Manchester encoded data stream from the TP receiver into NRZ data for the controller interface
by decoding the data and stripping off the SOI pulse. Since the clock and data recovery block has
already separated the clock and data from the TP receiver, the Manchester decoding process to NRZ
data is inherently performed by that block.
7.7.4 Clock and Data Recovery
Clock Recovery - 100 Mbps
Clock recovery is done with a PLL. If there is no valid data present on the TP inputs, the PLL is locked
to the 25 MHz TX25. When valid data is detected on the TP inputs with the squelch circuit and when
the adaptive equalizer has settled, the PLL input is switched to the incoming data on the TP input.
The PLL then recovers a clock by locking onto the transitions of the incoming signal from the twisted
pair wire. The recovered dock frequency is a 25 MHz nibble dock, and that clock is outputted on the
controller interface signal RX25.
Revision 1.92 (06-27-11)
28
DATASHEET
SMSC LAN91C111 REV C