C517A_99 Datasheet, PDF (57/218 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Reset / System Clock
C517A
5 Reset and System Clock Operation
5.1 Hardware Reset Operation
The hardware reset function incorporated in the C517A allows for an easy automatic start-up at a
minimum of additional hardware and forces the controller to a predefined default state. The
hardware reset function can also be used during normal operation in order to restart the device. This
is particularly done when the power down mode is to be terminated.
Additional to the hardware reset, which is applied externally to the C517A, there are two internal
reset sources, the watchdog timer and the oscillator watchdog. This chapter deals only with the
external hardware reset.
The reset input is an active low input. An internal Schmitt trigger is used at the input for noise
rejection. Since the reset is synchronized internally, the RESET pin must be held low for at least two
machine cycles (24 oscillator periods) while the oscillator is running. With the oscillator running the
internal reset is executed during the second machine cycle and is repeated every cycle until RESET
goes high again.
During reset, pins ALE and PSEN are configured as inputs and should not be stimulated or driven
externally. (An external stimulation at these lines during reset activates several test modes which
are reserved for test purposes. This in turn may cause unpredictable output operations at several
port pins).
At the RESET pin, a pullup resistor is internally connected to V_DD to allow a power-up reset with an
external capacitor only. An automatic power-up reset can be obtained when V_DD is applied by
connecting the reset pin to V_SS via a capacitor. After V_DD has been turned on, the capacitor must hold
the voltage level at the reset pin for a specific time to effect a complete reset.
Semiconductor Group
5-1