C517A_99 Datasheet, PDF (119/218 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C517A
Compare Timer
Overflow
CTF
Interrupt Logic
Comparator
Output
Circuit
P4.x/CMx
Compare Latch
TOC Loading
Control
"Write to CMLx"
Compare Register CMx
MCS01865
Figure 6-27
Compare Function of a CMx Register Assigned to the Compare Timer
Figure 6-27 shows a more detailed block diagram of a CMx register connected to the compare
timer. lt illustrates that the CPU can only access the special function register CMx; the actual
compare latch is, however, loaded at timer overflow. The timer overflow signal also sets an interrupt
request flag (CTF in register CTCON) which may be used to inform the CPU by an interrupt that a
new timer cycle has started and that the compare values for the next cycle may be programmed
from now on.
The activation of the TOC loading depends on a few conditions described in the following. A TOC
loading is performed only if the CMLx register has been changed by the CPU. A write instruction to
the low byte of the CMx register is used to enable the loading. The 8-bit architecture of the C517A
requires such a defined enable mechanism because 16-bit values are to be transferred in two
portions (= two instructions).
Imagine the following situation: one instruction (e.g. loading the low byte of the compare register) is
executed just before timer overflow and the other instruction (loading the high byte) after the
overflow. lf there were no "rule", the TOC loading would just load the new low byte into the compare
latch. The high byte - written after timer overflow - would have to wait till the next timer overflow.
The mentioned condition for TOC loading prevents such undesired behavior. lf the user writes the
high byte first then no TOC loading will happen before the low byte has been written - even if there
is a timer overflow in between. lf the user just intends to change the low byte of the compare latch
then the high byte may be left unaffected.
Semiconductor Group
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