C517A_99 Datasheet, PDF (55/218 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

External Bus Interface
C517A
condition is stored internally. After each 16th data byte the cumulated verify result (pass or fail) of
the last 16 verify operations is output at P3.5. This means that P3.5 stays at static level (low for fail
and high for pass) during the 16 bytes are checked. In ROM verification mode 2, the C517A must
be provided with a system clock at the XTAL pins.
Figure 4-6 shows an application example of an external circuitry which allows to verify a protected
ROM inside the C517A-4R in ROM verification mode 2. With RESET going inactive, the C517A-4R
starts the ROM verify sequence. Its ALE is clocking a 16-bit address counter. This counter
generates the addresses for an external EPROM which is programmed with the contents of the
internal (protected) ROM. The verify detect logic typically displays the pass/fail information of the
verify operation. P3.5 can be latched with the falling edge of ALE.
When the last byte of the internal ROM has been handled, the C517A-4R starts generating a PSEN
signal. This signal or the CY signal of the address counter indicate to the verify detect logic the end
of the internal ROM verification.
P3.5
Carry
ALE
CLK
15-Bit
2 kΩ
Address
Counter
S
C517A-4R
&
RESET
Port 0
EA
PSEN
&
VV_CCDD
Verify
Detect
Logic
V_{VCDC D}
Figure 4-6
ROM Verification Mode 2 - External Circuitry Example
Semiconductor Group
4-11
A0-A14
Compare
Code
ROM
D0-D7
CS OE
MCS03322