C517A_99 Datasheet, PDF (123/218 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C517A
6.3.5 Modulation Range in Compare Mode 0
In compare mode 0, a 100% variation of the duty cycle of a PWM signal cannot be reached. A time
portion of 1/(2ⁿ) of an n-bit timer period is always left over. This "spike" may either appear when the
compare register is set to the reload value (limiting the lower end of the modulation range) or it may
occur at the end of a timer period.
In a timer 2 / CCx register configuration in compare mode 0 this spike is divided into two halves: one
at the beginning when the contents of the compare register is equal to the reload value of the timer;
the other half when the compare register is equal to the maximum value of the timer register (here:
FFFFH). Please refer to figure 6-30 where the maximum and minimum duty cycle of a compare
output signal is illustrated. Timer 2 is incremented with the processor cycle (f_OSC/12), thus at 12 MHz
operating frequency, these spikes are both approx. 500 ns long.
CCHx/CCLx = 0000H or = CRCH/CRCL (maximum duty cycle)
P1.x
H
L
Appr. 1/2 of a Machine Cycle
CCHx/CCLx = FFFFH (minimum duty cycle)
Appr. 1/2 of a Machine Cycle
H
P1.x
L
MCT01851
Figure 6-30
Modulation Range of a PMW Signal Generated with a Timer 2 / CCx Register Combination in
Compare Mode 0
The following example shows how to calculate the modulation range for a PWM signal. For the
calculation with reasonable numbers, a reduction of the resolution to 8-bit is used. Otherwise (for
the maximum resolution of 16-bit) the modulation range would be so severely limited that it would
be negligible.
Example:
Timer 2 in auto-reload mode; contents of reload register CRC = FF00H
Restriction of modulation. range =
1
x 100% = 0.195%
256 x 2
This leads to a variation of the duty cycle from 0.195% to 99.805% for a timer 2 / CCx register
configuration when 8 of 16 bits are used.
Semiconductor Group
6-57