C517A_99 Datasheet, PDF (205/218 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Power Saving Modes
C517A
9.6 Software Power Down Mode
In the software power down mode, the RC osciillator and the on-chip oscillator which operates with
the XTAL pins is stopped. Therefore, all functions of the microcontroller are stopped and only the
contents of the on-chip RAM, XRAM and the SFR’s are maintained. The port pins, which are
controlled by their port latches, output the values that are held by their SFR’s. The port pins which
serve the alternate output functions show the values they had at the end of the last cycle of the
instruction which initiated the software power down mode. ALE and PSEN hold at logic low level
(see table 9-1).
In the software power down mode of operation, V_DD can be reduced to minimize power
consumption. It must be ensured, however, that is V_DD not reduced before the software power down
mode is invoked, and that V_DD is restored to its normal operating level before the software power
down mode is terminated.
The software power down mode can be terminated in three ways :
– An active reset signal. Using reset to leave software power down mode puts the
microcontroller with its SFRs into the reset state.
– A rising edge at PE/SWD. If this pin is rising during the software power down mode, the
microcontroller will go into the reset state.
Leaving software power down mode should not be done before V_DD is restored to its nominal
operating level.
9.6.1 Invoking Software Power Down Mode
If the software power down mode is to be used, the pin PE/SWD must be held low. The software
power down mode is entered by two consecutive instructions. The first instruction has to set the flag
bit PDE (PCON.1) and must not set bit PDS (PCON.6), the following instruction has to set the start
bit PDS (PCON.6) and must not set bit PDE (PCON.1). The hardware ensures that a concurrent
setting of both bits, PDE and PDS, does not initiate the software power down mode. Bits PDE and
PDS will automatically be cleared after having been set and the value shown by reading one of
these bits is always 0. This double instruction is implemented to minimize the chance of
unintentionally entering the software power down mode which could possibly ”freeze” the chip's
activity in an undesired status.
PCON is not a bit-addressable register, so the above mentioned sequence for entering the software
power down mode is obtained by byte-handling instructions, as shown in the following example:
ORL
ORL
PCON,#00000010B
PCON,#01000000B
;set bit PDE, bit PDS must not be set
;set bit PDS, bit PDE must not be set, enter power down
The instruction that sets bit PDS is the last instruction executed before going into software power
down mode.
9.6.2 Exit from Software Power Down Mode
If software power down mode is exit via a hardware reset, the microcontroller with its SFRs is put
into the hardware reset state and the content of RAM and XRAM are not changed. The reset signal
that terminates the software power down mode also restarts the RC oscillator and the on-chip
oscillatror. The reset operation should not be activated before V_DD is restored to its normal
operating level and must be held active long enough to allow the oscillator to restart and stabilize
(similar to power-on reset).
Semiconductor Group
9-7