C517A_99 Datasheet, PDF (54/218 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

External Bus Interface
C517A
4.6.2 Protected ROM Mode
If the ROM is protected, the ROM verification mode 2 as shown in figure 4-5 is used to verify the
contents of the ROM. The detailed timing characteristics of the ROM verification mode is shown in
the AC specifications in the C517A Data Sheet.
RESET
ALE
1. ALE Pulse
after Reset
Port 0
12 t _CLCL
6 t _CLCL
Latch
Data for
Addr. 0
P3.5
Inputs : ALE =V_SS
PSEN, EA = V_IH
RESET =
Latch
Data for Data for
Addr. 1 Addr. X-16-1
Latch
Data for
Addr. X-16
Latch
Data for
Addr. x-16+1
Low : Error
High : OK
MCT03222
Figure 4-5
ROM Verification Mode 2
ROM verification mode 2 is selected if the inputs PSEN, EA, and ALE are put to the specified logic
levels. With RESET going inactive, the ROM verification mode 2 sequence is started. The C517A
outputs an ALE signal with a period of 12 t_CLCL and expects data bytes at port 0. The data bytes at
port 0 are assigned to the ROM addresses in the following way :
1. Data Byte =
2. Data Byte =
3. Data Byte =
:
16. Data Byte =
:
content of internal ROM address 0000H
content of internal ROM address 0001H
content of internal ROM address 0002H
content of internal ROM address 000FH
The C517A-4R does not output any address information during the ROM verification mode 2. The
first data byte to be verified is always the byte which is assigned to the internal ROM address 0000H
and must be put onto the data bus with the falling edge of RESET. With each following ALE pulse
the ROM address pointer is internally incremented and the expected data byte for the next ROM
address must be delivered externally.
Between two ALE pulses the data at port 0 is latched (at 3 CLP after ALE rising edge) and compared
internally with the ROM content of the actual address. If an verify error is detected, the error
Semiconductor Group
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