C517A_99 Datasheet, PDF (101/218 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C517A
6.3.2.2 Operating Modes of the Compare Timers
The compare timer receives its input clock from a programmable prescaler which provides eight
input frequencies, ranging from f_OSC/2 up to f_OSC/256. This configuration allows a very high flexibility
concerning timer period length and input clock frequency. The prescaler ratio is selected by four bits
in the special function registers CTCON. Figure 6-16 shows the block diagram of the compare
timer.
f _OSC /2
3-Bit Prescaler
Compare Timer
/2 /4 /8 /16 /32 /64 /128
Control (CTCON)
16
To Compare
Circuitry
16-Bit Compare Timer
To Interrupt
CTF
Circuitry
16-Bit Reload (CTREL)
Overflow
MCB00783
Figure 6-16
Compare Timer Block Diagram
The compare timer is, once started, a free-running 16-bit timer, which upon overflow is
automatically reloaded by the content of the 16-bit reload register. This reload register is CTRELL
(compare timer reload register, low byte) and CTRELH (compare timer reload register, high byte).
An initial writing to the reload register CTRELL starts the corresponding compare timer. If a compare
timer is already running, a write to CTRELL again triggers an instantly reload of the timer, in other
words loads the timer in the cycle following the write instruction with the new count stored in the
reload registers CTRELH/CTRELL.
When the reload register is to be loaded with a 16-bit value, the high byte of the reload register
(CTRELH) must be written first to ensure a determined start or restart position. Writing to the low
byte (CTRELL) then triggers the actual reload procedure mentioned above. The 16-bit reload value
Semiconductor Group
6-35