C517A_99 Datasheet, PDF (126/218 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C517A
Please note that for CC registers 1 to 3 an interrupt is always requested when the compare signal
goes active.
The second configuration which should be noted is when compare functions are combined with
negative transition activated interrupts. lf the port latch of port P1.0 or P.1.4 contains a 1, the
interrupt request flags IEX3 or IEX2 will immediately be set after enabling the compare mode for the
CRC or CC4 register. The reason is that first the external interrupt input is controlled by the pin’s
level. When the compare option is enabled the interrupt logic input is switched to the internal
compare signal, which carries a low level when no true comparison is detected. So the interrupt
logic sees a 1-to-0 edge and sets the interrupt request flag.
An unintentional generation of an interrupt during compare initialization can be prevented if the
request flag is cleared by software after the compare is activated and before the external interrupt
is enabled.
6.3.6.2 Interrupt Enable Bits of the Compare/Capture Unit
This section summarizes all CCU related interrupt enable control bits. The interrupt enable bits for
the compar timer and the compare match and capture interrupt capture are located in the SFR
IEN2:
Special Function Register IEN2 (Address 9AH)
MSB
Bit No. 7
6
5
4
3
2
9AH
–
– ECR ECS ECT ECMP
Reset Value : XX0000X0B
LSB
1
0
– ES1 IEN2
Bit
ECR
ECS
ECT
ECMP
The shaded bits are not used for CCU interrupt control.
Function
COMCLR register compare match interrupt enable
If ECR = 0, the COMCLR compare match interrupt is disabled.
COMSET register compare match interrupt enable
If ECS = 0, the COMSET compare match interrupt is disabled.
Enable compare timer interrupt
If ECT = 0, the compare timer overflow interrupt is disabled.
CM0-7 register compare match interrupt
If ECMP = 0, the CM0-7 compare match interrupt is disabled.
Semiconductor Group
6-60