C517A_99 Datasheet, PDF (188/218 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Interrupt System
C517A
Execution proceeds from that location until the RETI instruction is encountered. The RETI
instruction informs the processor that the interrupt routine is no longer in progress, then pops the
two top bytes from the stack and reloads the program counter. Execution of the interrupted program
continues from the point where it was stopped. Note that the RETI instruction is very important
because it informs the processor that the program left the current interrupt priority level. A simple
RET instruction would also have returned execution to the interrupted program, but it would have
left the interrupt control system thinking an interrupt was still in progress. In this case no interrupt of
the same or lower priority level would be acknowledged.
7.4 External Interrupts
The external interrupts 0 and 1 can be programmed to be level-activated or negative-transition
activated by setting or clearing bit IT0 or IT1, respectively, in register TCON. lf ITx = 0 (x = 0 or 1),
external interrupt x is triggered by a detected low level at the INTx pin. lf ITx = 1, external interrupt
x is negative edge-triggered. In this mode, if successive samples of the INTx pin show a high in one
cycle and a low in the next cycle, interrupt request flag lEx in TCON is set. Flag bit lEx then requests
the interrupt.
lf the external interrupt 0 or 1 is level-activated, the external source has to hold the request active
until the requested interrupt is actually generated. Then it has to deactivate the request before the
interrupt service routine is completed, or else another interrupt will be generated.
The external interrupts 2 and 3 can be programmed to be negative or positive transition-activated
by setting or clearing bit I2FR or I3FR in register T2CON. lf IxFR = 0 (x = 2 or 3), external interrupt
x is negative transition-activated. lf IxFR = 1, external interrupt is triggered by a positive transition.
The external interrupts 4, 5, and 6 are activated by a positive transition. The external timer 2 reload
trigger interrupt request flag EXF2 will be activated by a negative transition at pin P1.5/T2EX but
only if bit EXEN2 is set.
Since the external interrupt pins (INT2 to INT6) are sampled once in each machine cycle, an input
high or low should be held for at least 12 oscillator periods to ensure sampling. lf the external
interrupt is transition-activated, the external source has to hold the request pin low (high for INT2
and INT3, if it is programmed to be negative transition-active) for at least one cycle, and then hold
it high (low) for at least one cycle to ensure that the transition is recognized so that the
corresponding interrupt request flag will be set (see figure 7-5). The external interrupt request flags
will automatically be cleared by the CPU when the service routine is called.
Semiconductor Group
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