C517A_99 Datasheet, PDF (124/218 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C517A
In a compare timer/CMx register configuration, the compare output is set to a constant high level if
the contents of the compare registers are equal to the reload register (CTREL). The compare output
shows a high level for one timer clock period when a CMx register is set to FFFFH. Thus, the duty
cycle can be varied from 0.xx% to 100% depending on the resolution selected. In figure 6-31 the
maximum and minimum duty cycle of a compare output signal is illustrated. One clock period of the
compare timer is equal to one machine state (= 2 oscillator periods) if the prescaler is off. Thus, at
12 MHz system clock the spike is approx. 166.6 ns long.
a) CMHx/CMLx = CTREL (maximum duty cycle)
P4.x
H
L
b) _{CCMTRHExL/C=/MFLFxF=FFHFFFH (minimum duty cycle)}
One machine state or two oscillator cycle
H
P4.x
L
MCT01854
Figure 6-31
Modulation Range of a PWM Signal Generated with a Compare Timer/CMx Register
Combination
Semiconductor Group
6-58