C517A_99 Datasheet, PDF (175/218 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Interrupt System
C517A
7.1 Interrupt Registers
7.1.1 Interrupt Enable Registers
Each interrupt vector can be individually enabled or disabled by setting or clearing the
corresponding bit in the interrupt enable registers IEN0, IEN1, and IEN2. Register IEN0 also
contains the global disable bit (EAL), which can be cleared to disable all interrupts at once. Some
interrupts sources have further enable bits (e.g. EXEN2). Such interrupt enable bits are controlled
by specific bits in the SFRs of the corresponding peripheral units. This section describes the
locations and meanings of the interrupt enable bits in detail.
After reset the enable bits of the interrupt enable registers IEN0 to IEN2 are set to 0. That means
that the corresponding interrupts are disabled.
The SFR IEN0 includes the enable bits for the external interrupts 0 and 1, the timer 0,1, and 2
interrupts, the serial interface 0 interrupt, and the general interrupt enable control bit EAL.
Special Function Register IEN0 (Address A8H)
Reset Value : 00H
Bit No.
A8H
MSB
AF_H
EAL
AE_H
WDT
AD_H
ET2
AC_H
ES0
AB_H
ET1
AA_H
EX1
A9_H
ET0
LSB
A8_H
EX0
IEN0
The shaded bit is not used for interrupt control
Bit
Function
EAL
Enable/disable all interrupts.
If EA=0, no interrupt will be acknowledged.
If EA=1, each interrupt source is individually enabled or disabled by setting or
clearing its enable bit.
ET2
Timer 2 interrupt enable.
If ET2 = 0, the timer 2 interrupt is disabled.
ES0
Serial channel 0 interrupt enable
If ES0 = 0, the serial channel interrupt 0 is disabled.
ET1
Timer 1 overflow interrupt enable.
If ET1 = 0, the timer 1 interrupt is disabled.
EX1
External interrupt 1 enable.
If EX1 = 0, the external interrupt 1 is disabled.
ET0
Timer 0 overflow interrupt enable.
If ET0 = 0, the timer 0 interrupt is disabled.
EX0
External interrupt 0 enable.
If EX0 = 0, the external interrupt 0 is disabled.
Semiconductor Group
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