C517A_99 Datasheet, PDF (204/218 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Power Saving Modes
C517A
9.5 Slow Down Mode Operation
In some applications, where power consumption and dissipation is critical, the controller might run
for a certain time at reduced speed (e.g. if the controller is waiting for an input signal). Since in
CMOS devices there is an almost linear dependence of the operating frequency and the power
supply current, a reduction of the operating frequency results in reduced power consumption.
In the slow down mode all signal frequencies that are derived from the oscillator clock are divided
by 8. This also includes the clock output signal at pin P1.6/CLKOUT. Further, if the slow down mode
is used pin PE/SWD must be held low.
The slow down mode is activated by setting the bit SD in SFR PCON. If the slow down mode is
enabled, the clock signals for the CPU and the peripheral units are reduced to 1/8 of the nominal
system clock rate. The controller actually enters the slow down mode after a short synchronization
period (max. two machine cycles). The slow down mode is disabled by clearing bit SD.
The slow down mode can be combined with the idle mode by performing the following double
instruction sequence:
ORL PCON,#00000001B
ORL PCON,#00110000B
; preparing idle mode: set bit IDLE (IDLS not set)
; entering idle mode combined with the slow down mode:
; (IDLS and SD set)
There are two ways to terminate the combined Idle and Slow Down Mode :
– The idle mode can be terminated by activation of any enabled interrupt. The CPU operation
is resumed, the interrupt will be serviced and the next instruction to be executed after the RETI
instruction will be the one following the instruction that sets the bits IDLS and SD.
Nevertheless the slow down mode keeps enabled and if required has to be disabled by
clearing the bit SD in the corresponding interrupt service routine or after the instruction that
sets the bits IDLS and SD.
– The other possibility of terminating the combined idle and slow down mode is a hardware
reset. Since the oscillator is still running, the hardware reset has to be held active for only two
machine cycles for a complete reset.
Semiconductor Group
9-6