C517A_99 Datasheet, PDF(105/218 Page) Siemens Semiconductor Group

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C517A_99 Datasheet, PDF (105/218 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

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On-Chip Peripheral Components

C517A

6.3.3.2 Compare Mode 1

In compare mode 1, the software adaptively determines the transition of the output signal. This

mode can only be selected for compare registers assigned to timer 2. lt is commonly used when

output signals are not related to a constant signal period (as in a standard PWM generation) but

must be controlled very precisely with high resolution and without jitter. In compare mode 1, both

transitions of a signal can be controlled. Compare outputs in this mode can be regarded as high

speed outputs which are independent of the CPU activity.

lf compare mode 1 is enabled and the software writes to the appropriate output latch at the port, the

new value will not appear at the output pin until the next compare match occurs. Thus, it can be

choosen whether the output signal has to make a new transition (1-to-0 or 0-to-1, depending on the

actual pin-level) or should keep its old value at the time when the timer value matches the stored

compare value.

Figure 6-19 shows a functional diagram of a port cicuit configuration in compare mode 1. In this

mode the port circuit consists of two separate latches. One latch (which acts as a "shadow latch")

can be written under software control, but its value will only be transferred to the port latch (and thus

to the port pin) when a compare match occurs.

Port Circuit

Compare Register

Circuit

Compare Reg.

16 Bit

Comparator

16 Bit

Timer Register

Compare

Match

Internal

Bus

Write to

Latch

Read Latch

VVCDCD

Port

Shadow

Port

Latch

CLK

Timer Circuit

Read Pin

MCS02662

Figure 6-19

Compare Function of Compare Mode 1

Note that the double latch structure is transparent as long as the internal compare signal is active.

While the compare signal is active, a write operation to the port will then change both latches. This

may become important when timer 2 is driven with a slow input clock. In this case the compare

signal could be active for many machine cycles in which the CPU could unintentionally change the

contents of the port latch.

A read-modify-write instruction will read the user-controlled "shadow latch" and write the modified

value back to this "shadow-latch". A standard read instruction will - as usual - read the pin of the

corresponding compare output.

Semiconductor Group

6-39

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