C517A_99 Datasheet, PDF (163/218 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C517A
Bit
ADCL
Function
A/D converter clock prescaler selection
ADCL selects the prescaler ratio for the A/D conversion clock f_ADC.
Depending on the clock rate f_OSC of the C517A, f_ADC must be adjusted in
a way that the resulting f_ADC clock is less or equal 2 MHz.
The prescaler ratio is selected according the following table :
ADCL
0
1
Prescaler Ratio
divide by 4 (default after reset)
divide by 8
Note :Generally, before entering the power-down mode, an A/D conversion in progress must be
stopped. If a single A/D conversion is running, it must be terminated by polling the BSY bit or
waiting for the A/D conversion interrupt. In continuous conversion mode, bit ADM must be
cleared and the last A/D conversion must be terminated before entering the power-down
mode.
A single A/D conversion is started by writing to SFR ADDATL with dummy data. A continuous
conversion is started under the following conditions :
– By setting bit ADM during a running single A/D conversion
– By setting bit ADM when at least one A/D conversion has occured after the last reset
operation.
– By writing ADDATL with dummy data after bit ADM has been set before (if no A/D conversion
has occured after the last reset operation).
When bit ADM is reset by software in continuous conversion mode, the just running A/D conversion
is stopped after its end.
Semiconductor Group
6-97