C517A_99 Datasheet, PDF (130/218 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C517A
6.4.2 Operation of the MDU
The MDU can be regarded as a special coprocessor for multiplication, division and shift. Its
operations can be divided into three phases (see figure 6-32):
1) Loading the MDx registers
2) Executing the calculation
3) Reading the result from the MDx registers
During phase two, the MDU works on its own parallelly to the CPU. Execution times of the above
table refer to this phase. Because of the fast operation and the determined execution time for
C517A’s instructions, there is no need for a busy flag. The CPU may execute a determined number
of instructions before the result is fetched. The result and the remainder of an operation may also
be stored in the MDx registers for later use.
Phase one and phase three require CPU activity. In these phases the CPU has to transfer the
operands and fetch the results.
1st Write (MD0)
Last Write (MD5 or ARCON)
First Read
(MD0)
Last Read
(MD3 or MD5)
Phase 1
Load Registers
Time
Phase 2
Calculate
Phase 3
Read Registers
MCD00787
Figure 6-32
Operating Phases of the MDU
The MDU has no dedicated instruction register (only for shift and normalize operations, register
ARCON is used in such a way). The type of calculation the MDU has to perform is selected following
the order in which the MDx registers are written to (see table 6-10). This mechanism also reduces
execution time spent for controlling the MDU. Hence, a special write sequence selects an operation.
The MDU monitors the whole write and read-out sequence to ensure that the CPU has fetched the
result correctly and was not interrupted by another calculation task.
Thus, a complete operation lasts from writing the first byte of the operand in phase 1 until reading
the last byte of the result in phase 3.
Semiconductor Group
6-64