C517A_99 Datasheet, PDF (127/218 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C517A
6.3.6.3 Interrupt Flags of the Compare/Capture Unit
This section handles the CCU related compare match interrupt flags. The timer 2 and compare timer
overflow interrupt flags (TF2 and CTF) are described in detail in section 6.3.1.1 and 6.3.2.1.
The compare timer match interrupt occurs on a compare match of the CM0 to CM7 registers with
the compare timer when compare mode 1 is selected for the corresponding channel. There are 8
compare match interrupt flags available in SFR IRCON1 which are or-ed together for a single
interrupt request. Thus, a compare match interrupt service routine has to check which compare
match has requested the compare match interrupt. The ICMPx flags must be cleared by software.
Only if timer 2 is assigned to the CMx registers (compare mode 0), an ICMPx request flag is set by
every match in the compare channel. When the compare timer is assigned to the CMx registers
(compare mode 1), an ICMPx request flag will not be set by a compare match event.
Special Function Register IRCON1 (Address D1H)
Reset Value : 00H
MSB
LSB
Bit No. 7
6
5
4
3
2
1
0
D1H ICMP7 ICMP6 ICMP5 ICMP4 ICMP3 ICMP2 ICMP1 ICMP0
IRCON1
Bit
ICMP7 - 0
Function
Compare timer match with register CM7 - CM0 interrupt flags
ICMPx is set by hardware when a compare match of the compare timer with the
compare register CMx occurs but only if the compare function for CMx has been
enabled. ICMPx must be cleared by software (CMSEL.x = 0 and CMEN.x = 1).
Semiconductor Group
6-61