C517A_99 Datasheet, PDF (120/218 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C517A
Summary of the TOC loading capability :
– The CMx registers are - when assigned to the compare timer - protected from direct loading
by the CPU. A register latch couple provides a defined load time at timer overflow.
– Thus, the CPU has a full timer period to load a new compare value: there is no danger of
overwriting compare values which are still needed in the current timer period.
– When writing a 16-bit compare value, the high byte should be written first since the write-to-
low-byte instruction enables a 16-bit wide TOC loading at next timer overflow.
– lf there was no write access to a CMx low byte then no TOC loading will take place.
– Because of the TOC loading, all compare values written to CMx registers are only activated
in the next timer period.
Initializing the Compare Register/Compare Latch Circuit
Normally when the compare function is desired the initialization program would just write to the
compare register (called ’register latch’). The compare latch itself cannot be accessed directly by a
move instruction, it is exclusively loaded by the timer overflow signal.
In some very special cases, however, an initial loading of the compare latch could be desirable. lf
the following sequence in table 6-7 is observed during initialization then latches, the register and
the compare latch, can be loaded before the compare mode is enabled.
Table 6-7
Compare Register/Latch Initializing Sequence
Step Action
Comment
1 Select compare mode 1 (CMSEL.x = 0). This is also the default value after reset.
2 Move the compare value for the first timer In compare mode 1 latch is loaded directly
period to the compare register CMx (high after a write-to-CMLx. Thus the value slips
byte first).
directly into the compare latch.
3 Switch on compare mode 0 (CMSEL.x = 1) Now select the right compare mode.
4 Move the compere value for the second
timer period to the compare register.
The register latch is loaded; this value is
used after the first timer overflow.
5 Enable the compare function (CMEN.x = 1) –
6 Set up the prescaler for the compare timer. –
7 Set specific compare output to low level
(CLR P4.x)
The compare output is switched to low level.
8 Start the compare timer with a desired value Compare function is initialized; the output
(write-to-CTREL)
will oscillate.
Semiconductor Group
6-54