C517A_99 Datasheet, PDF (118/218 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C517A
6.3.4.4.1 CMx Registers Assigned to the Compare Timer
Every CMx register assigned to the compare timer as a time base operates in compare mode 0 and
uses a port 4 pin as an alternate output function.
The "Timer Overflow Controlled" (TOC) Loading
There is one great difference between a CMx register and the other previously described compare
registers: compare outputs controlled by CMx registers have no dedicated interrupt function. They
use a "timer overflow controlled loading" (further on called "TOC loading") to reach the same
performance as an interrupt controlled compare. To show what this "TOC loading" is for, it will be
explained more detailed in the following:
The main advantage of the compare function in general is that the controller’s outputs are precisely
timed by hardware, no matter which task is running on the CPU. This in turn means that the CPU
normally does not know about the timer count. So, if the CPU writes to a compare register only in
relation to the program flow, then it could easily be that a compare register is overwritten before the
timer had the chance to reach the previously loaded compare value. Hence, there must be
something to "synchronize" the loading of the compare registers to the running timer circuitry. This
could either be an interrupt caused by the timer circuitry (as described before) or a special hardware
circuitry.
Thus "TOC-Ioading" means that there is dedicated hardware in the CCU which synchronizes the
loading of the compare registers CMx in such a way that there is no loss of compare events. lt also
relieves the CPU of interrupt load.
A CMx compare register in compare mode 0 consists of two latches. When the CPU tries to access
a CMx register it only addresses a register latch and not the actual compare latch which is
connected to the comparator circuit. The contents of the register latch may be changed by the CPU
at any time because this change would never affect the compare event for the current timer period.
The compare latch (the "actual" latch) holds the compare value for the present timer period. Thus
the CPU only changes the compare event for the next timer period since the loading of the latch is
performed by the timer overflow signal of the compare timer.
This means for an application which uses several PWM outputs that the CPU does not have to
serve every single compare line by an individual interrupt. lt only has to watch the timer overflow of
the compare timer and may then set up the compare events of all compares for the next timer
period. This job may take the whole current timer period since the TOC loading prevents
unintentional overwriting of the actual (and prepared) value in the compare latch.
Semiconductor Group
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