C517A_99 Datasheet, PDF (192/218 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Fail Safe Mechanisms
C517A
8.1.1 Input Clock Selection
The input clock rate of the watchdog timer is derived from the system clock of the C517A. There is
a prescaler available, which is software selectable and defines the input clock rate. This prescaler
is controlled by bit WDTPSEL in the SFR WDTREL. Tabel 8-1 shows resulting timeout periods at
f_OSC = 12 and 24 MHz.
Special Function Register WDTREL (Address 86H)
Reset Value : 00H
MSB
LSB
Bit No. 7
6
5
4
3
2
1
0
86H
WDT
PSEL
Reload Value
WDTREL
Bit
WDTPSEL
WDTREL.6 - 0
Function
Watchdog timer prescaler select bit.
When set, the watchdog timer is clocked through an additional divide-by-
16 prescaler.
Seven bit reload value
for the high-byte of the watchdog timer. This value is loaded to WDTH
when a refresh is triggered by a consecutive setting of bits WDT and
SWDT.
Table 8-1
Watchdog Timer Time-Out Periods (WDTPSEL = 0)
WDTREL
00H
80H
7FH
Time-Out Period
f_OSC = 12 MHz
65.535 ms
f_OSC = 24 MHz
32.768 ms
1.1 s
0.55 s
512 µs
256 µs
Comments
This is the default value
Maximum time period
Minimum time period
Semiconductor Group
8-2