C517A_99 Datasheet, PDF (152/218 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C517A
6.5.3.2 Mode 1/Mode B, 8-Bit UART (Serial Interfaces 0 and 1)
Ten bits are transmitted (through TXD0 or TXD1), or received (through RXD0 or RXD1): a start bit
(0), 8 data bits (LSB first), and a stop bit (1). On reception through RXD0, the stop bit goes into RB80
(S0CON), on reception through RXD1, RB81 (S1C0N) stores the stop bit.
The baud rate for serial interface 0 is determined by the timer 1 overflow rate or by the internal baud
rate generator of serial interface 0. Serial interface 1 receives the baud rate clock from its own baud
rate generator.
Figure 6-38 shows a simplified functional diagram of the both serial channels in mode 1 or mode
B, respectively. The associated timing is illustrated in figure 6-39.
Transmission is initiated by any instruction that uses S0BUF/S1BUF as a destination register. The
"write-to-S0BUF/S1BUF" signal also loads a 1 into the 9th bit position of the transmit shift register
and flags the TX control block that a transmission is requested. Transmission actually commences
at S1P1 of the machine cycle following the next roll-over in the divide-by-16 counter (thus, the bit
times are synchronized to the divide-by-16 counter, not to the "write-to-S0BUF/S1BUF" signal).
The transmission begins with activation of SEND, which puts the start bit to TXD0/TXD1. One bit
time later, DATA is activated, which enables the output bit of the transmit shift register to TXD0/
TXD1. The first shift pulse occurs one bit time after that.
As data bits shift out to the right, zeros are clocked in from the left. When the MSB of the data byte
is at the output position of the shift register, then the 1 that was initially loaded into the 9th position
is just to the left of the MSB, and all positions to the left of that contain zeros. This condition flags
the TX control to do one last shift and then deactivate SEND and set TI0/Tl1. This occurs at the 10th
divide-by-16 rollover after "write-to-S0BUF/S1BUF".
Reception is initiated by a detected 1-to-0 transition at RXD0/RXD1. For this purpose RXD0/RXD1
is sampled at a rate of 16 times whatever baud rate has been established. When a reception is
detected, the divide-by-16 counter is immediately reset, and 1FFH is written into the input shift
register, and reception of the rest of the frame will proceed.
The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th and 9th counter states
of each bit time, the bit detector samples the value of RXD0/RXD1. The value accepted is the value
that was seen in at least 2 of the 3 samples. This is done for noise rejection. lf the value accepted
during the first bit time is not 0, the receive circuits are reset and the unit goes back looking for
another 1-to-0 transition. This is to provide rejection of false start bits. lf the start bit proves valid, it
is shifted into the input shift register, and reception of the rest of the frame will proceed.
As data bits come from the right, 1’s shift out to the left. When the start bit arrives at the leftmost
position in the shift register (which in mode 1/B is a 9-bit register), it flags the RX control block to do
one last shift. The signal to load S0BUF/S1BUF and RB80/RB81, and to set RI0/Rl1 will be
generated if, and only if, the following conditions are met at the time the final shift pulse is generated:
1) RI0/Rl1 = 0, and
2) either SM20/SM21 = 0 or the received stop bit = 1
lf one of these two conditions is not met the received frame is irretrievably lost. lf both conditions are
met, the stop bit goes into RB80/RB81, the 8 data bits go into S0BUF/S1BUF, and RI0/Rl1 is
activated. At this time, no matter whether the above conditions are met or not, the unit goes back
to looking for a 1-to-0 transition in RxD0/RxD1.
Semiconductor Group
6-86