C517A_99 Datasheet, PDF (187/218 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

Interrupt System
C517A
Note that if an interrupt of a higher priority level goes active prior to S5P2 in the machine cycle
labeled C3 in figure 7-4 then, in accordance with the above rules, it will be vectored to during C5
and C6 without any instruction for the lower priority routine to be executed.
Thus, the processor acknowledges an interrupt request by executing a hardware-generated LCALL
to the appropriate servicing routine. In some cases it also clears the flag that generated the
interrupt, while in other cases it does not. Then this has to be done by the user’s software. The
hardware clears the external interrupt flags IE0 and IE1 only if they were transition-activated. The
hardware-generated LCALL pushes the contents of the program counter onto the stack (but it does
not save the PSW) and reloads the program counter with an address that depends on the source of
the interrupt being vectored to, as shown in table 7-2.
Table 7-2
Interrupt Source and Vectors
Interrupt Source
External Interrupt 0
Timer 0 Overflow
External Interrupt 1
Timer 1 Overflow
Serial Channel 0
Timer 2 Overflow / Ext. Reload
A/D Converter
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
External Interrupt 6
Serial Channel 1
Compare Match Interupt of
Compare Registers CM0-CM7
assigned to Timer 2
Compare Timer Overflow
Compare Match Interupt of
Compare Register COMSET
Compare Match Interupt of
Compare Register COMCLR
Interrupt Vector Address
0003H
000BH
0013H
001BH
0023H
002BH
0043H
004BH
0053H
005BH
0063H
006BH
0083H
0093H
Interrupt Request Flags
IE0
TF0
IE1
TF1
RI0 / TI0
TF2 / EXF2
IADC
IEX2
IEX3
IEX4
IEX5
IEX6
RI1 / TI1
ICMP0 - ICMP7
009BH
CTF
00A3H
ICS
00ABH
ICR
Semiconductor Group
7-17