C517A_99 Datasheet, PDF (111/218 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C517A
6.3.4.2 Timer 2 - Capture Function with Registers CRC, CC1 to CC4
Each of the four compare/capture registers CC1 to CC4 and the CRC register can be used to latch
the current 16-bit value of the timer 2 registers TL2 and TH2. Two different modes are provided for
the capture function. In capture mode 0, an external event latches the timer 2 contents to a
dedicated capture register. In capture mode 1, a capture event will occur when the low order byte
of the dedicated 16-bit capture register is written to. This capture mode is provided to allow the
software to read the timer 2 contents "on-the-fly".
In capture mode 0, the external event causing a capture is
– for CC1 to CC3 registers :
– for the CRC and CC4 register :
A positive transition at pins CC1 to CC3 of port 1
A positive or negative transition at the corresponding pins,
depending on the status of the bits I3FR and I2FR in SFR
T2CON. lf the edge flags are cleared, a capture occurs in
response to a negative transition; if the edge flags are set
a capture occurs in response to a positive transition at pins
P1.0/ INT3/ CC0 and P1.4/ INT2/ CC4.
In both cases the appropriate port 1 pin is used as input and the port latch must be programmed to
contain a one (1). The external input is sampled in every machine cycle. When the sampled input
shows a low (high) level in one cycle and a high (low) in the next cycle, a transition is recognized.
The timer 2 content is latched to the appropriate capture register in the cycle following the one in
which the transition was identified.
In capture mode 0 a transition at the external capture inputs of registers CC0 to CC4 will also set
the corresponding external interrupt request flags IEX2 to IEX6. lf the interrupts are enabled, an
external capture signal will cause the CPU to vector to the appropriate interrupt service routine.
In capture mode 1 a capture occurs in response to a write instruction to the low order byte of a
capture register. The write-to-register signal (e.g. write-to-CRCL) is used to initiate a capture. The
value written to the dedicated capture register is irrelevant for this function. The timer 2 contents will
be latched into the appropriate capture register in the cycle following the write instruction. In this
mode no interrupt request will be generated.
Figures 6-23 and 6-24 show functional diagrams of the capture function of timer 2. Figure 6-23
illustrates the operation of the CRC or CC4 register, while figure 6-24 shows the operation of the
compare/capture registers CC1 to CC3.
The two capture modes are selected individually for each capture register by bits in SFR CCEN
(compare/capture enable register) and CC4EN (compare/capture 4 enable register). That means,
in contrast to the compare modes, it is possible to simultaneously select capture mode 0 for one
capture register and capture mode 1 for another register.
Semiconductor Group
6-45