C517A_99 Datasheet, PDF (134/218 Pages) Siemens Semiconductor Group – 8-Bit CMOS Microcontroller

On-Chip Peripheral Components
C517A
Table 6-11
Programming a Shift or Normalize Operation
Operation
First write
Last write
First read
Last read
Normalize, Shift Left, Shift Right
MD0
MD1
MD2
MD3
ARCON
least significant byte
.
.
most significant byte
start of conversion
MD0
MD1
MD2
MD3
least significant byte
.
.
most significant byte
6.4.5 The Overflow Flag
An overflow flag is provided for some exceptions during MDU calculations. There are three cases
where flag MDOV ARCON.6 is set by hardware:
– Division by zero
– Multiplication with a result greater then 0000 FFFFH
(= auxiliary carry of the lower 16bit)
– Start of normalizing if the most significant bit of MD3 is set (MD3.7 = 1).
Any operation of the MDU which does not match the above conditions clears the overflow flag. Note
that the overflow flag is exclusively controlled by hardware. lt cannot be written to.
6.4.6 The Error Flag
The error flag, bit MDEF in register ARCON is provided to indicate whether one of the arithmetic
operations of the MDU (multiplication, division, normalize, shift left/right) has been restarted or
interrupted by a new operation.
This can possibly happen e.g. when an interrupt service routine interrupts the writing or reading
sequence of the arithmetic operation in the main program and starts a new operation. Then the
contents of the corresponding registers are indeterminate (they would normally show the result of
the last operation executed).
In this case the error flag can be used to indicate whether the values in the registers MD0 to MD5
are the expected ones or whether the operation must be repeated. For a multiplication/division, the
error flag mechanism is automatically enabled with the first write instruction to MD0 (phase 1).
According to the above described programming sequences, this is the first action for every type of
calculation. The mechanism is disabled with the final read instruction from MD3 or MD5 (phase 3).
Every instruction which rewrites MD0 (and therefore tries to start a new calculation) in phases 1
through 3 of the same process sets the error flag.
The same applies for any shift operation (normalize, shift left/right). The error flag is set if the user’s
program reads one of the relevant registers (MD0 to MD3) or if it writes to MD0 again before the
shift operation has been completed.
Semiconductor Group
6-68