K4B1G0446C Datasheet, PDF (59/63 Pages) Samsung semiconductor – 1Gb C-die DDR3 SDRAM Specification

K4B1G04(08/16)46C
1Gb DDR3 SDRAM
Data Setup, Hold and Slew Rate Derating:
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet tDS(base) and tDH(base) value (see
Table 57) to the ∆ tDS and ∆tDH (see Table 58) derating value respectively. Example: tDS (total setup time) = tDS(base) + ∆tDS.
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIH(ac)min.
Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing of VIL(ac)max
(see Figure 27). If the actual signal is always earlier than the nominal slew rate line between shaded ’VREF(dc) to ac region’, use nominal slew rate for
derating value. If the actual signal is later than the nominal slew rate line anywhere
between shaded ’VREF(dc) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see
Figure 29).
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max and the first crossing of VREF(dc).
Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(dc)min and the first crossing of VREF(dc)
(see Figure 28). If the actual signal is always later than the nominal slew rate line between shaded ’dc level to VREF(dc) region’, use nominal slew rate for
derating value. If the actual signal is earlier than the nominal slew rate line anywhere between shaded ’dc to VREF(dc) region’, the slew rate of a tangent
line to the actual signal from the dc level to VREF(dc) level is used for derating value (see Figure 30).
For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC (see Table 59).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(ac) at the time of the rising clock
transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rates in between the values listed in the tables the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization
[ Table 57 ] Data Setup and Hold Base-Value
[ps]
tDS(base)
tDH(base)
DDR3-800
75
150
DDR3-1066
25
100
DDR3-1333
-10
65
DDR3-1600
TBD
TBD
reference
V_IH/L(ac)
V_IH/L(dc)
Note : AC/DC referenced for 1V/ns DQ-slew rate and 2 V/ns DQS slew rate)
[ Table 58 ] Derating values DDR3-800/1066 tIS/tIH-ac/dc based
∆tDS, ∆tDH Derating [ps] AC/DC based^a
DQS,DQS Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4V/ns
∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH ∆tDS ∆tDH
2.0
88
50
88
50
88
50
-
-
-
-
-
-
1.5
59
34
59
34
59
34
67
45
-
-
-
-
1.0
0
0
0
0
0
0
8
8
16
16
-
-
DQ _0.9
-
Slew
rate
0.8
-
V/ns ^0.7
-
-
-2
-4
-2
-4
6
4
14
12
22
20
-
-
-
-6
-10
2
-2
10
6
18
14
-
-
-
-
-
-3
-8
5
0
13
8
0.6
-
-
-
-
-
-
-
-
-1
-10
7
-2
0.5
-
-
-
-
-
-
-
-
-
-
-11 -16
0.4
-
-
-
-
-
-
-
-
-
-
-
-
Note : a. Cell contents shaded in red are defined as ’not supported’.
1.2V/ns
∆tDS ∆tDH
-
-
-
-
-
-
-
-
26
24
21
18
15
8
-2
-6
-30 -26
1.0V/ns
∆tDS ∆tDH
-
-
-
-
-
-
-
-
-
-
29
34
23
24
6
10
-22 -10
[ Table 59 ] Required time t_VAC above VIH(ac) {blow VIL(ac)} for valid transition
Slew Rate[V/ns]
>2.0
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
<0.5
t_VAC[ps]
min
75
57
50
38
34
29
22
13
0
0
max
-
-
-
-
-
-
-
-
-
-
Page 59 of 63
Rev. 1.0 June 2007